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?2000 integrated device technology, inc. dsc 3199/7 1

true dual-ported memory cells which allow simultaneous access of the same memory location high-speed access ? military: 25/35/55ns (max) ? industrial: 25ns (max.) ? commercial: 20/25/35/55ns (max.) low-power operation ? idt7027s active: 750mw (typ.) standby: 5mw (typ.) ? idt7027l active: 750mw (typ.) standby: 1mw (typ.) separate upper-byte and lower-byte control for bus matching capability. dual chip enables allow for depth expansion without high-speed 32k x 16 dual-port static ram idt7027s/l external logic idt7027 easily expands data bus width to 32 bits or more using the master/slave select when cascading more than one device m/ s = v ih for busy output flag on master, m/ s = v il for busy input on slave busy and interrupt flags on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port ttl-compatible, single 5v (10%) power supply available in 100-pin thin quad flatpack (tqfp) and 108-pin ceramic pin grid array (pga) industrial temperature range ( ? 40 c to +85 c) is available for selected speeds notes: 1. busy is an input as a slave (m/ s =v il ) and an output as a master (m/ s =v ih ). 2. busy and int are non-tri-state totem-pole outputs (push-pull). i/o control address decoder 32kx16 memory array 7027 arbitration interrupt semaphore logic ce 0l oe l r/ w l a 14l a 0l a 14l a 0l sem l int l (2) busy l (1,2) lb l ce 0l oe l ub l i/o control address decoder ce 0r oe r r/ w r a 14r a 0r a 14r a 0r sem r int r (2) busy r (1,2) lb r r/ w r oe r ub r m/ s (2) ce 1l ce 0r ce 1r 3199 drw 01 i/o ce 1r ce 1l 8-15l i/o i/o 0-7r i/o 8-15r 0-7l r/ w l .
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 2
the idt7027 is a high-speed 32k x 16 dual-port static ram, designed to be used as a stand-alone 512k-bit dual-port ram or as a combination master/slave dual-port ram for 32-bit-or-more word systems. using the idt master/slave dual-port ram approach in 32- bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. the device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by the chip enables ( ce 0 and ce 1 ) permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 750mw of power. the idt7027 is packaged in a 100-pin thin quad flatpack (tqfp) and a 108-pin ceramic pin grid array (pga). military grade product is manufactured in compliance with the latest revision of mil-prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100999897969594939291908988878685848382818079787776 idt7027pf pn100-1 (4) 100-pin tqfp top view (5) gnd oe r r/ w r sem r ce 1r ce 0r nc nc gnd a 12r a 13r a 11r a 10r a 9r a 14r nc i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r i/o 15r gnd ub r lb r 3199 drw 02 i/o 15l gnd oe l r/ w l sem l ce 1l ce 0l vcc nc a 14l a 13l nc nc a 12l a 11l a 10l a 9l i/o 10l i/o 11l i/o 12l i/o 13l i/o 14l ub l lb l gnd i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 0 r i / o 0 l g n d i / o 2 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 3 l i / o 1 r i / o 7 r n c i / o 8 r i / o 9 r i / o 8 l i / o 9 l i / o 6 r a 7 r a 8 l a 7 l a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r i n t r b u s y r m / s b u s y l i n t l n c a 0 l a 2 l a 3 l a 5 l a 6 l a 1 l a 4 l a 8 r g n d v c c i / o 1 l v c c g n d .
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 3
!" # notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. package body is approximately 1.21 in x 1.21 in x .16 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 14l a 0r - a 14r address i/o 0l - i/o 15l i/o 0r - i/o 15r data input/output sem l sem r semaphore enable ub l ub r upper byte select lb l lb r lower byte select int l int r interrupt flag busy l busy r busy flag m/ s master or slave select v cc power gnd ground 3199 tbl 01 3199 drw 03 80 77 74 72 69 68 65 63 60 83 78 76 73 70 67 64 61 59 84 56 86 87 88 90 91 92 94 95 97 96 100 99 103 101 105 104 2 1 5 4 7 8 10 12 13 17 16 21 19 25 22 28 24 32 31 34 35 37 39 40 44 43 48 46 52 49 55 51 idt7027g g108-1 (4) 108-pin pga top view (5) ab cde fghj k l m 81 57 54 53 82 79 75 71 66 62 58 50 33 36 38 41 42 45 47 3 6 9 111415182023 29 30 26 27 85 89 93 98 102 106 107 108 12 11 10 09 08 07 06 05 04 03 02 01 index gnd oe r r/ w r sem r ce 1r ce 0r nc nc gnd a 12r a 13r a 11r a 10r a 9r gnd oe l r/ w l sem l ce 1l ce 0l vcc nc a 14l a 13l nc nc a 12l a 11l a 10l a 9l i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 0r gnd vcc i/o 0l i/o 1l gnd i/o 2l i/o 4l i/o 5l i/o 6l i/o 7 l i/o 3l i/o 1r i/o 7r nc i/o 8r i/o 9r i/o 8l i/o 9l vcc a 6r a 5r a 4r a 3r a 2r a 1r a 0r int r busy r m/ s busy l int l nc a 0l gnd a 2l a 3l a 5l a 6l a 1l a 4l a 8r a 7r a 8l a 7l a 14r nc i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r i/o 15r i/o 10l i/o 11l i/o 12l i/o 13l i/o 14l gnd ub r lb r ub l lb l gnd nc nc nc nc nc nc nc nc i/o 15l .
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 4 notes: 1. chip enable references are shown above with the actual ce 0 and ce 1 levels, ce is a reference only. 2. port "a" and "b" references are located where ce is used. 3. "h" = v ih and "l" = v il . $%$&'(%) & $%$&''(# * +,-. notes: 1. a 0l ? a 14l a 0r ? a 14r. 2. refer to chip enable truth table. $%$&'''(/% +,-. notes: 1. there are eight semaphore flags written to via i/o 0 and read from all the i/os (i/o 0 __ i/o 15 ). these eight semaphore flags are addressed by a 0 -a 2 . 2. refer to chip enable truth table. ce ce 0 ce 1 mode l v il v ih port selected (ttl active) < 0.2v > v cc -0.2v port selected (cmos active) h v ih x port deselected (ttl inactive) xv il port deselected (ttl inactive) > v cc -0.2v x p o rt de s e le c te d (cm o s inac tiv e ) x< 0.2v port deselected (cmos inactive) 3199 tbl 02 inputs (1) outputs mode ce (2) r/ w oe ub lb sem i/o 8-15 i/o 0-7 hxxxxhhigh-zhigh-zdeselected: power-down x x x h h h high-z high-z both bytes deselected llxlhhdata in high-z write to upper byte only l l x h l h high-z data in write to lower byte only llxllhdata in data in write to both bytes lhllhhdata out high-z read upper byte only lhlhlhhigh-zdata out read lower byte only lhlllhdata out data out read both bytes x x h x x x high-z high-z outputs disabled 3199 tbl 03 inputs (1) outputs mode ce (2) r/ w oe ub lb sem i/o 8-15 i/o 0-7 hhlxx ldata out data out read data in semaphore flag xhlhhldata out data out read data in semaphore flag h xxxldata in data in write i/o 0 into semaphore flag x xhhldata in data in write i/o 0 into semaphore flag lxxlxl ______ ______ not allowed lxxxll ______ ______ not allowed 3199 tbl 04
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 5

$ 01230"%4 $56#7 )

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68%6 $ ,/9: + : 02":;< note: 1. at vcc < 2.0v, input leakages are undefined. +
,,6 , =6 $ ,/9: & =+ notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 10%. notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv represents the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. 2. industrial temperature: for other speeds packages and powers, contact your sales office. symbol rating commercial & industrial military unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature unde r bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c i out dc output current 50 50 ma 3199 tbl 05 grade ambient temperature gnd vcc military -55 o c to+125 o c0v 5.0v + 10% commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 3199 tbl 06 symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 3199 tbl 08 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 3199 tbl 07 symbol parameter test conditions 7027s 7027l unit min. max. min. max. |i li | input leakage current (1 ) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = 4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 3199 tbl 09
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 6 )

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68%6 $ ,/9: + >? : 02":;< notes: 1. 'x' in part numbers indicates power rating (s or l). 2. v cc = 5v, t a = +25 c, and are not production tested. i ccdc = 120ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/ t rc, and using ? ac test conditions ? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". 6. refer to chip enable truth table. 7. industrial temperature: for other speeds, packages and powers contact your sales office. 7027x20 com'l only 7027x25 com'l, ind & military 7027x35 com'l & military 7027x55 com'l & military symbol parameter test condition version typ. (2) max. typ. (2) max. typ. (2) max. typ. (2) max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled sem = v ih f = f max (3) com'l s l 185 185 325 285 180 170 305 265 160 160 295 255 150 150 270 230 ma mil & ind s l ____ ____ ____ ____ 170 170 345 305 160 160 335 295 150 150 310 270 i sb1 standby current (bo th ports - ttl level inp uts) ce l = ce r = v ih sem r = sem l = v ih f = f max (3) com'l s l 55 55 90 70 40 40 85 60 30 30 85 60 20 20 85 60 ma mil & ind s l ____ ____ ____ ____ 40 40 100 80 30 30 100 80 20 20 100 80 i sb2 standby current (one port - ttl level inp uts) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (3) sem r = sem l = v ih com'l s l 120 120 215 185 105 105 200 170 95 95 185 155 85 85 165 135 ma mil & ind s l ____ ____ ____ ____ 105 105 230 200 95 95 215 185 85 85 195 165 i sb3 full standby current (bo th ports - all cmos level inputs) bo th ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) sem r = sem l > v cc - 0.2v com'l s l 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 ma mil & ind s l ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - all cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) sem r = sem l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, active port outputs disable d, f = f max (3) com'l s l 115 115 190 160 100 100 170 145 90 90 160 135 80 80 135 110 ma mil & ind s l ____ ____ ____ ____ 100 100 200 175 90 90 190 165 80 80 175 150 3199 tbl 1 0
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 7 $ , )

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68% 6 $ ,/9: + @> notes: . 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . 4. 'x' in part numbers indicates power rating (s or l). 5. refer to chip enable truth table. 6. industrial temperature: for other speeds, packages and powers contact your sales office. figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig. dinput pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns max. 1.5v 1.5v figures 1 and 2 3199 tbl 11 3199 drw 04 893 ? 30pf 347 ? 5v data out busy int 893 ? 5pf* 347 ? 5v data out 7027x20 com'l only 7027x25 com'l, ind. & military 7027x35 com'l & military 7027x55 com'l & military symbol parameter min.max.min.max.min.max.min.max.unit read cycle t rc read cycle time 20 ____ 25 ____ 35 ____ 55 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ____ 55 ns t ace chip enable access time (3 ) ____ 20 ____ 25 ____ 35 ____ 55 ns t abe byte enable access time (3 ) ____ 20 ____ 25 ____ 35 ____ 55 ns t aoe output enable access time ____ 12 ____ 13 ____ 20 ____ 30 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 15 ____ 25 ns t pu chip enable to power up time (2,5) 0 ____ 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2,5) ____ 20 ____ 25 ____ 35 ____ 50 ns t sop semaphore flag update pulse ( oe or sem )10 ____ 12 ____ 15 ____ 15 ____ ns t saa semaphore address access time ____ 20 ____ 25 ____ 35 ____ 55 ns 3199 tbl 12
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 8 .8 +,9
2 $ a*b a* a notes: 1. timing depends on which signal is asserted last, ce , oe , lb , or ub . 2. timing depends on which signal is de-asserted first ce , oe , lb , or ub . 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simu ltaneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t bdd . 5. sem = v ih . 6. refer to chip enable truth table. t rc r/ w ce addr t aa oe ub , lb 3199 drw 05 (4) t ace (4) t aoe (4) t abe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) (6) ce 3199 drw 06 t pu i cc i sb t pd 50% 50% (6) .
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 9 notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. refer to chip enable truth table. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. 'x' in part numbers indicates power rating (s or l). 6. industrial temperature: for other speeds, packages and powers contact your sales office. )

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68% 6 $ ,/9: 2> symbol parameter 7027x20 com'l only 7027x25 com'l, ind & military 7027x35 com'l & military 7027x55 com'l & military unit min. max. min. max. min. max. min. max. wri te cycle t wc write cycle time 20 ____ 25 ____ 35 ____ 55 ____ ns t ew chip enable to end-of-write (3 ) 15 ____ 20 ____ 30 ____ 45 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ 45 ____ ns t as address set-up time (3 ) 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 15 ____ 20 ____ 25 ____ 40 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 ____ 15 ____ 30 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 15 ____ 25 ns t dh data hold time (4 ) 0 ____ 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 12 ____ 15 ____ 15 ____ 25 ns t ow output active from end-of-write (1 , 2 ,4 ) 0 ____ 0 ____ 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ 5 ____ ns 3199 tbl 13
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 10 $ .8 .9
# "+- w ,$ 2c notes: 1. r/ w or ce or ub and lb = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from stead y state with the output test load (figure 2). 8. if oe = v il during r/w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. 10. refer to chip enable truth table. $ .8 .9
# " ce ub lb ,$ 2 r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) ub or lb 3199 drw 07 (9) ce or sem (9,10) (7) (3) 3199 drw 08 t wc t as t wr t dw t dh address data in r/ w t aw t ew ub or lb (3) (2) (6) ce or sem (9,10) (9)
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 11 $ .8 /% +,.$ )%/, $ .8 /% . @ notes: 1. ce = v ih or ub and lb = v ih for the duration of the above timing (both write and read cycle), refer to chip enable truth table. 2. "data out valid" represents all i/o's (i/o 0 -i/o 15 ) equal to the semaphore value. notes: 1. d or = d ol = v il , ce r = ce l = v ih , or both ub & lb = v ih (refer to chip enable truth table). 2. all timing is the same for left and right ports. port ? a ? may be either left or right port. port ? b ? is the opposite from port ? a ? . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied, there is no guarantee which side will be granted the semaphore flag. sem 3199 drw 09 t aw t ew t sop i/o 0 valid address t saa r/ w t wr t oh t ace valid address data in valid data out t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe valid (2) sem "a" 3199 drw 10 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side (2) "b"
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 12 notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual), or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. 'x' in part numbers indicates power rating (s or l). 7. industrial temperature: for other speeds, packages and powers contact your sales office. )

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68% 6 $ ,/9: + >? 7027x20 com'l only 7027x25 com'l, ind. & military 7027x35 com'l & military 7027x55 com'l & military symbol parameter min.max.min.max.min.max.min.max.unit busy timing (m/ s =v ih ) t baa busy access time from address match ____ 20 ____ 20 ____ 20 ____ 45 ns t bda busy disable time from address not matched ____ 20 ____ 20 ____ 20 ____ 40 ns t bac busy access time from chip enable low ____ 20 ____ 20 ____ 20 ____ 40 ns t bdc busy access time from chip enable high ____ 17 ____ 17 ____ 20 ____ 35 ns t aps arbitration priority set-up time (2 ) 5 ____ 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3 ) ____ 30 ____ 30 ____ 35 ____ 40 ns t wh write hold after busy (5 ) 15 ____ 17 ____ 25 ____ 25 ____ ns busy timing (m/ s =v il ) t wb busy input to write (4 ) 0 ____ 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5 ) 15 ____ 17 ____ 25 ____ 25 ____ ns port-to-port delay timing t wdd write pulse to data delay (1 ) ____ 45 ____ 50 ____ 60 ____ 80 ns t ddd write data valid to re ad data de lay (1 ) ____ 30 ____ 35 ____ 45 ____ 65 ns 3199 tbl 14
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 13 $ .8 .a% * * +, , busy - s 0 : 'd @2 notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the "slave" version. $ .8 .a% busy - s 0: '7 notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il (refer to chip enable truth table). 3. oe = v il for the reading port. 4. if m/ s = v il (slave), busy is an input. then for this example busy "a" = v ih and busy "b" input is shown above. 5. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 3199 drw 11 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa 3199 drw 12 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (2) (3) (1) .
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 14 .8 busy & 9
,&9,,
% $ - s 0: 'd notes: 1. all timing is the same for left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from port ? a ? . 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 3. refer to chip enable truth table. .8 busy & ,&9 ce $ - s 0: 'd notes: 1. 'x' in part numbers indicates power rating (s or l). 2. industrial temperature: for other speeds, packages and powers contact your sales office. )

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68% 6 $ ,/9: + 3199 drw 13 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 3199 drw 14 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" 7027x20 com'l only 7027x25 com'l, ind & military 7027x35 com'l & military 7027x55 com'l & military symbol parameter min.max.min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 20 ____ 20 ____ 25 ____ 40 ns t inr interrupt reset time ____ 20 ____ 20 ____ 25 ____ 40 ns 3199 tbl 15
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 15 .8 ' $ 2 $%$&':e' @ notes: 1. all timing is the same for left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from port ? a ? . 2. see the interrupt truth table iv. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 5. refer to chip enable truth table. notes: 1. assumes busy l = busy r =v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. refer to chip enable truth table. 3199 drw 15 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 3199 drw 16 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2) left port right port function r/ w l ce l oe l a 14l -a 0l int l r/ w r ce r oe r a 14r -a 0r int r l lx7fffxxxx x l (2) set right int r flag xxx x xxll7fffh (3) reset right int r flag xxx x l (3) l l x 7ffe x set left int l flag xll7ffeh (2) x x x x x re se t left int l flag 3199 tbl 16
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 16 notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt7027 are push-pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of the actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of the actual logic level on the pin. 4. refer to chip enable truth table. notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt7027. 2. there are eight semaphore flags written to via i/o 0 and read from all the i/o's (i/o 0 -i/o 15 ). these eight semaphores are addressed by a 0 -a 2 . 3. ce = v ih , sem = v il , to access the semaphores. refer to the semaphore read/write control truth table.

the idt7027 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt7027 has an automatic power down feature controlled by ce 0 and ce 1 . the ce 0 and ce 1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. ' if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7ffe (hex), where a write is defined as ce r = r/ w r = v il per truth table iv. the left port clears the interrupt through access of address location 7ffe when ce l = oe l = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7fff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location 7fff. the message (16 bits) at 7ffe or 7fff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 7ffe and 7fff are not used as mail-boxes by ignoring the interrupt, but as part of the random access memory. refer to truth table iv for the interrupt operation. $%$&:'e)= /%
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$%$&:e ,,& @ inputs outputs function ce l ce r a ol -a 14l a or -a 14r busy l (1 ) busy r (1 ) xxno match h h normal hxmatchh hnormal xhmatchh hnormal ll match (2) (2) write inhibit (3 ) 3199 tbl 17 functions d 0 - d 15 left d 0 - d 15 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 3199 tbl 18
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 17 97
busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ? busy ? . the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be pre- vented to a port by tying the busy pin for that port low. the busy outputs on the idt7027 ram in master mode, are push- pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. figure 3. busy and chip enable routing for both width and depth expansion with idt7027 rams. .,%)= a%97
-/89 when expanding an idt7027 ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt7027 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. /% the idt7027 is a fast dual-port 32k x 16 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port sram to claim a privilege over the other processor for functions defined by the system designer ? s software. as an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual- port sram or any other shared resource. the dual-port sram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non- semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port sram. these devices have an automatic power-down feature controlled by ce the dual-port sram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table ii where ce and sem = v ih . systems which can best use the idt7027 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt7027's hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt7027 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high- speed systems. d a%/% . the semaphore logic is a set of eight latches which are independent of the dual-port sram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ? token passing allocation. ? in this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore ? s status or remove its request for that semaphore to 3199 drw 17 master dual port ram busy r ce 0 master dual port ram busy r slave dual port ram busy r slave dual port ram busy r ce 1 ce 1 ce 0 a 15 busy l busy l busy l busy l busy l busy r
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial and commercial temperature ranges 18 d 3199 drw 18 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read . perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt7027 in a separate memory space from the dual-port sram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table vi). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thorough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side ? s output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see truth table vi). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two semaphore request latches feed into a semaphore flag. whichever latch is first to present a zero to the figure 4. idt7027 semaphore logic semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side ? s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side ? s request latch. the second side ? s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simulta- neous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
6.42 idt7027s/l high-speed 32k x 16 dual-port static ram military, industrial an d commercial temperature ranges 19 6, ' note: 1. industrial temperature range is available on selected tqfp packages in standard power. for other speeds, packages and powers contact your sales office. a power 999 speed a package a process/ temperature range blank i (1) b commercial (0c to +70c) industrial (-40c to + 85c) military (-55c to +125c) compliant to mil-prf-38535 qml pf g 100-pin tqfp (pn100-1) 108-pin pga (g108-1) 20 25 35 55 s l standard power low power xxxxx device type 512k (32k x 16) dual-port ram 7027 idt 3199 drw 19 commercial only commercial, industrial & military commercial & military commercial & military speed in nanoseconds corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. %
d 9 1/15/99: initiated datasheet document history converted to new format cosmetic and typographical corrections pages 2 and 3 added additional notes to pin configurations 5/19/99: pages 4 and 16 fixed typographical errors 6/3/99: changed drawing format page 1 corrected dsc number 11/10/99: replaced idt logo 5/22/00: page 5 increased storage temperature parameter clarified t a parameter page 6 dc electrical parameters ? changed wording from "open" to "disabled" changed 200mv to 0mv in notes

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